1. Field of the Invention
The present invention relates to a plasma display panel, and more particularly, to a plasma display apparatus and driving method thereof, which can control rising and falling times (durations) of data pulses applied to address electrodes in an address period, thereby reducing noise generation, stabilizing address discharges, and preventing electrical damage to driving circuits.
2. Background of the Related Art
Generally, a plasma display panel includes barrier ribs formed between a front substrate and a rear substrate. Together, the barrier ribs and the front and rear substrates form cells. Each of the cells is filled with a primary discharge gas such as neon (Ne), helium (He) or a mixed gas comprising Ne and He. In addition, each cell contains an inert gas comprising a small amount of xenon. If the inert gas is discharged using a high voltage, vacuum ultraviolet rays are generated. The ultraviolet rays excite light-emitting phosphors formed between the barrier ribs to display an image. Plasma display panels can be made thin and slim, and have thus been in the spotlight as one of the next-generation of display devices.
FIG. 1 is a perspective view illustrating the construction of a related art plasma display panel. In FIG. 1, the related art plasma display panel includes a front substrate 100 in which a plurality of pairs of display electrodes, which are formed by a plurality of pairs of scan electrodes 102 and sustain electrodes 103, are arranged on a front glass 101 that serves as a display surface on which the images are displayed. The plasma display panel also includes a rear substrate 110, in which a plurality of address electrodes 113 cross the plurality of display electrodes, is arranged on a rear glass 111 forming a rear surface. The front substrate 100 and the rear substrate 110 are parallel to each other with a predetermined distance therebetween.
The front substrate 100 includes the pairs of the scan electrodes 102 and the sustain electrodes 103 to perform discharge against the other mutually and maintain emission in one discharge cell. The scan electrode 102 and the sustain electrode 103 each has a transparent electrode “a” made of a transparent ITO material and a bus electrode “b” made of a metal material, and the scan and sustain electrodes 102, 103 are formed in pairs. The scan electrodes 102 and the sustain electrodes 103 are covered with one or more dielectric layers 104 to limit a discharge current and to provide insulation among the electrode pairs. A protection layer 105, on which magnesium oxide (MgO) is deposited to facilitate a discharge condition, is formed on the dielectric layer 104.
On the rear substrate 110, barrier ribs 112—of a stripe type or well type—forming a plurality of discharge spaces, i.e., discharge cells, are arranged in a parallel manner. Further, a plurality of address electrodes 113, which perform address discharging to generate the vacuum ultraviolet rays, are disposed parallel to the barrier ribs 112. Red (R), green (G) and blue (B) phosphors 114, which emit visible rays for image display upon address discharging, are coated on a top surface of the rear substrate 110. A low dielectric layer 115 to protect the address electrodes 113 is formed between the address electrodes 113 and the phosphors 114.
A method for implementing image gray scales using the related art plasma display panel will now be described with reference to FIG. 2. As shown in FIG. 2, in order to represent the gray scales of the image in the related art plasma display panel, one frame period is divided into a plurality of sub-fields each having a different number of emission. Each sub-field is subdivided into a reset period for initializing all cells, an address period for selecting discharged cells, and a sustain period for implementing gray scales according to the number of discharges. For example, if it is desired to display an image with 256 gray scales, a frame period (16.67 ms) corresponding to 1/60 second is divided into eight sub-fields SF1 to SF8 as shown in FIG. 2. Each of the eight sub-fields SF1 to SF8 is subdivided into the reset, address and sustain periods as indicated above.
The reset period and the address period of each of the sub-fields are the same for every sub-field. Address discharge for selecting cells to be discharged is generated due to a voltage difference between the address electrodes 113 and transparent electrodes “a” of the scan electrodes 102. The sustain period increases by a ratio of 2n (where, n=0, 1, 2, 3, 4, 5, 6, 7) in each of the sub-fields. Because the sustain period is varied in each sub-field, the gray scale of an image is represented by adjusting the sustain period of each of the sub-fields, i.e., by adjusting the number of sustain discharges. A driving waveform in the method of driving the related art plasma display panel will be described below with reference to FIG. 3.
Referring to FIG. 3, the plasma display panel is driven in the following manner: each sub-field is divided into a reset period for initializing all cells, an address period for selecting cells to be discharged, a sustain period for maintaining the discharge of the selected cells, and an erase period for erasing wall charges within discharged cells.
The reset period is further divided into a set-up period and a set-down period. In the set-up period of the reset period, a ramp-up waveform Ramp-up is applied to all scan electrodes 102 simultaneously. A weak dark discharge is generated within discharge cells of the entire screen due to the ramp-up waveform. The set-up discharge causes positive polarity wall charges to be accumulated on the address electrodes 113 and the sustain electrodes 103 and also causes negative polarity wall charges to be accumulated on the scan electrodes 102.
In the set-down period of the reset period, a ramp-down waveform Ramp-down is applied to all scan electrodes 102. The ramp-down waveform is such that the voltage on the scan electrodes 102 falls from a positive voltage that is below the peak voltage of the ramp-up waveform to a voltage below the ground level voltage GND. The ramp-down waveform applied to the scan electrodes 102 causes a weak erase discharge to occur within the cells. As a result, excessive wall charges formed on the scan electrodes 102 are sufficiently erased. The set-down discharge also causes wall charges to remain within the cells uniformly to the degree in which stable address discharge can be generated.
In the address period of each sub-field, while a negative scan pulse is sequentially applied to the scan electrodes 102, a positive data pulse—synchronized with the negative scan pulse—is applied to the address electrodes 113. As a voltage difference between the scan pulse and the data pulse and a wall voltage generated in the reset period are added, address discharging is generated within the discharge cells to which the data pulses are applied. Further, wall charges of the degree in which discharge can be generated when a sustain voltage Vs is applied are formed within the cells selected by the address discharging. A positive polarity voltage Vz is applied to the sustain electrodes 103 so that erroneous discharge is not generated with the scan electrode 102 by reducing a voltage difference with the scan electrode 102 during the address period.
In the sustain period, a sustain pulse Sus is alternately applied to the scan electrodes 102 and the sustain electrodes 103. In the cells selected by address discharging, a sustain discharge, i.e., a display discharge, is generated between the scan electrodes 102 and the sustain electrodes 103 whenever each sustain pulse is applied as the wall voltage within the cells and the sustain pulse are added.
After the sustain discharge is completed, in the erase period, an erase ramp waveform Ramp-ers, which has a narrow pulse width and a low voltage level, is applied to the sustain electrodes 103 so that wall charges remaining in the cells of the entire screen are erased.
In this related art driving waveform, application time points of the data pulses applied to the address electrodes 113 in the address period will be described with reference to FIG. 4. As shown in FIG. 4, the data pulse applied in the address period rises at a tilt and also falls at a tilt. This related art data pulse has a voltage-rising time or duration (tup) and a voltage-falling time or duration (tdown) that are relatively short. For example, the tup and tdown times of the related art data pulse can be approximately 20 ns.
Furthermore, the related art data pulse is the same for all address electrodes. This situation will be described with reference to FIG. 5, which is a view for explaining the voltage-rising time and the voltage-falling time of data pulses applied to the address electrodes during the address period in the related art driving waveform.
As shown in FIG. 5, the data pulses with identical voltage-rising times tup and identical voltage-falling times tdown are applied to all address electrodes X1 to Xm. In FIG. 5, the data pulses applied to address electrodes X1, X2, X3 . . . Xm all begin rising at a time point t1 and then reach the highest point at a time point t2. That is, the voltage-rising time tup is t2−t1 for all electrodes. Furthermore, the data pulses all begin falling at a time point t3 and then reach the lowest point at a time point t4. That is, the voltage-falling time tdown is t4−t3 for all electrodes.
As such, in the related art, the tup and tdown times of the data pulses are relatively short and same for all data pulses applied to all the address electrodes. As a result, a significant amount of noise is generated. Noise generation due to the data pulses will be described with reference to FIG. 6.
From FIG. 6, it can be seen that a relatively large amount of noise is generated in the data pulses applied to the address electrodes. That is, when the data pulse rises, some noise is generated in the direction of the rising voltage (overshoot). When the data pulse falls, some noise is generated in the direction of the falling voltage (undershoot). The noise is generated due to the coupling of the data pulses applied to address electrodes at points where the voltage of the data pulses abruptly change, i.e. at points where the voltage falls and where the voltage rises.
If a difference between the highest value of rising noise and the lowest value of falling noise, i.e., the amount of noise Vr, becomes excessive, the address discharge generated during the address period becomes unstable. As a result, driving efficiency of plasma display panel is reduced. Also, electrical damage to the data drive ICs that supply the data pulses to the address electrodes can occur. Components having high voltage ratings can be used to prevent such electrical damage to the data drive ICs. However, utilizing such components increases the cost of production.